1. Field of the Invention
The present invention relates to a semiconductor device integrating a plurality of power elements on a single chip and a method of producing same. More particularly, the present invention relates to a semiconductor device wherein the respective power elements are electrically isolated by means of pn isolation and a method of producing same.
2. Description of the Related Arts
Conventionally, a semiconductor device formed on a pn junction isolation substrate, as shown in FIG. 8, includes a plurality of power elements and a control circuit thereof on a single chip. However, a semiconductor device employing a pn junction isolation substrate as shown in FIG. 8 may not operate properly because of parasitic transistors formed via an isolation region between mutually adjacent power elements and between power elements and a logic portion as indicated in FIG. 9. In order to prevent this, conventional devices increase the width of the isolation region between elements. For example, if the withstand voltage is set at 60V and the doping concentration of the first semiconductor substrate is set at 1.times.10.sup.15 cm.sup.-3, it is necessary to set the current amplification rate h.sub.FE of the parasitic npn transistor to 10.sup.-6 or less to prevent parasitism, but to do this, the foregoing interval (the width of the isolation region) is required to be approximately 100 .mu.m. Because of this, there exists the disadvantage of an increase in overall element size.
It is also known to provide another p type region or guard ring between the isolation region and the power elements to reduce the h.sub.FE of parasitic npn transistors produced between power elements to prevent parasitic transistors in pn isolation. However, a region for disposition of the guard ring becomes necessary. The region required for isolation is equal to or greater than the case wherein a guard ring is not employed. As a result, there exists the disadvantage of an increase in overall element size in the same manner as in the semiconductor device shown in FIG. 9.
In order to avoid the foregoing disadvantage of element enlargement, formation of a semiconductor device employing an isolation substrate as shown in FIG. 10 has been performed. In this device, there exists, for example, an article integrating an up-drain type lateral DMOS employing a complete SOI substrate which has a buried oxide in a whole wafer and isolating between adjacent elements with trenches as indicated in FIG. 10.
In the semiconductor device shown in FIG. 10, because isolation between elements is not performed by means of an isolation region or a guard ring, parasitic transistors are not produced, and there is no disadvantage of enlargement of elements. However, the heat-radiating performance is poor because elements are structured in a partition which is completely enclosed by silicon dioxide of poor thermal conductivity. Furthermore in the case wherein a power element is formed in this partition, there exists the disadvantage of a reduction of the upper limit for usage temperature.
Moreover, a structure eliminating the silicon dioxide at the bonding interface in consideration of heat-radiating performance as shown in FIG. 11 is known, but there still exists the disadvantage of faulty operation caused by parasitic transistors.
In short, it has not been possible to obtain a semiconductor device which prevents faulty operation due to parasitic transistors while ensuring heat-radiation performance, and which also has no overall element enlargement.